The present invention relates generally to computers and specifically to video random access memories (RAMs) that are competitively addressed both by CPUs and video controllers.
Description of Related Art
FIG. 1 illustrates a prior art computer system comprised of a central processing unit (CPU) 10 that is connected to a system bus 11 and outputs a CPU cycle code to a signal line 12. A command decoder 20 uses an input from signal line 12 and address information from bus 11 (not shown connected for simplicity) to generate a VRAM read signal 21 and write signal 22. A display unit 30 associated with the computer system is coupled to bus 11 and will respond to read and write signals 21 and 22. Display unit 30 is a plug-in board and has a video controller 40 that is coupled to a display bus 41 and a video channel 42. A priority arbiter 50 chooses whether to connect bus 11 or bus 41 to a VRAM bus 51. A display VRAM 60 stores information to be interpreted by video controller 40 for output on a display device 70. The system of FIG. 1 suffers from a conflict between access requests from video controller 40 and CPU 10 to VRAM 60. If priority arbiter 50 gives preference to access requests from CPU 10 then glitches will appear on the screen of display device 70 when video controller 40 starves for data. If priority is given to video controller 40, then CPU 10 will be forced to execute wait states (which can slow the whole system down).
FIG. 2 is a system which is similar to that of FIG. 1, but has included a first-in-first out (FIFO) write buffer 155 that solves, in part, delays caused to a CPU 110 when a video controller 140 has priority and CPU 110 is attempting a write. Write buffer 155 will buffer write requests to a VRAM 160 and will give CPU 110 an early acknowledgment. However, if write buffer 155 fills up, CPU 110 will again have to wait.
FIG. 3 is a typical system and is similar to those of FIGS. 1 and 2, but a random access memory (RAM) 290 and a read only memory (ROM) 291 are coupled to a bus 211, and a priority arbiter 250 is set up to give access priority to a video controller 240. The current design practice in the industry is to give the video controller priority over the CPU so as to avoid glitches on the screen of the display, but that has the effect of making the CPU wait for sometimes excessively long periods during some video controller accesses. RAM 290 is 640K bytes and is mapped into addresses 00000H to 09FFFFH (H=hexadecimal). Command decoder 220 outputs a signal 292 for RAM reads and a signal 293 for RAM writes. VRAM 260 is 128K bytes and is mapped into addresses 0A0000H to 0BFFFFH, which is just above the space for RAM 290. ROM 291 is 128K bytes and comprises a basic input/output system (BIOS) program. A signal 294 from decoder 220 is asserted for CPU read commands to ROM 291 that are within the address range of 0E0000H to 0FFFFFH. Command decoder 220 outputs a signal 221 for reads of VRAM 260 and a signal 222 for writes to VRAM 260.
It is therefore an object of the present invention to provide a technique for speeding up the reading of VRAM by a CPU through the reduction and/or elimination of wait states.